Kartik Anand

About Me

Hey there !

I’m Kartik Anand from Delhi, India. Currently, I’m a first year graduate student in the department of Computer Science at the University of Wisconsin-Madison. I’m broadly interested in the fields of Programming Languages and Compilers.

Before coming here, I was employed with Synopsys Inc. where I worked on developing logic synthesis tools. Logic Synthesis refers to the process of converting HDL (Hardware description languages) to gate level net list, in a sense, synthesis tools are your compilers for Verilog, VHDL, and System Verilog family of languages.

I like to make small fully contained side projects from time to time, particularly to learn new programming languages, web frameworks, and interesting programming paradigms. This website is a place to host and show off my silly side projects, and write on things that people may find interesting and helpful.

You may contact me through the below mentioned links:

Personal email : me [at] kartikanand.com or kartikanand1992 [at] gmail.com
Official email : kt [at] cs.wisc.edu

This website is a modified version of Indigo theme for Jekyll and is deployed on Github Pages.

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